The disclosed embodiments relate to a semiconductor memory device, and more particularly, to a single data rate (SDR) semiconductor memory device and a memory system having the same in which power consumption is reduced by making a cycle time of a data strobe signal larger than a cycle time of a clock signal.
Generally, a single data rate (SDR) semiconductor memory device outputs data in synchronization with a rising edge of a clock signal. The SDR semiconductor memory device needs a data strobe signal in order to minimize a skew between a plurality of input/output data signals.
The data strobe signal is toggled in synchronization with the clock signal, and as a cycle time of the data strobe signal is reduced, power consumption is increased. Accordingly, a larger cycle time of the data strobe signal than a cycle time of the clock signal is desirable.